The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a dual metal nitride landing pad for embedded high performance magnetoresistive random access memory (MRAM) devices.
MRAM is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin dielectric layer. One of the two plates is a permanent magnetic set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. Such a configuration is known as magnetic tunnel junction (MTJ).
For high performance MRAM based on perpendicular MTJ structures, well defined interfaces and interface control are essential. MTJ structures typically include a cobalt (Co)-based synthetic anti-ferromagnetic (SAF), a cobalt-iron-boron (CoFeB)-based reference layer, a magnesium oxide (MgO)-based tunnel barrier, a CoFeB-based free layer, and capping layers containing, for example, tantalum (Ta) and/or ruthenium (Ru). Embedded MTJ structures are usually formed by patterning of blanket MTJ stacks.
Also, landing pads for MRAM devices are required to be very uniform with very low surface roughness, i.e., the dielectric recessed around a metal landing pad must be less than 2 nm. Typically, chemical mechanical polishing (CMP) is used to create a damascene tantalum nitride (TaN) landing pad. However, CMP non-uniformity between isolated, wide pitch MRAM devices and dense, narrow pitch ground rule lines results in either ground rule line-to-line shorts, or excessive dielectric recess around the landing pads.
In view of the above, there is need to provide a landing pad for embedded high performance MRAM devices which can avoid the drawbacks mentioned above for conventional MRAM landing pads.